Performance of VLSI Engines for Lattice Computations
Steven D. Kugelmass
Richard Squier
Kenneth Steiglitz
Department of Computer Science, Princeton University,
Princeton, NJ 08544, USA
Abstract
We address the problem of designing and building efficient custom VLSI-based processors to do computations on large multi-dimensional lattices. The design tradeoffs for two architectures which provide practical engines for lattice updates are derived and analyzed. We find that I/O constitutes the principal bottleneck of processors designed for lattice computations, and we derive upper bounds on throughput for lattice updates based on Hong and Kung's graph-pebbling argument that models I/O. In particular, we show that 
, where 
is the site update rate, 
is the main memory bandwidth, 
is the processor storage, and 
is the dimension of the lattice.
